"CoreConnect" and "AMBA" are the two prominent bus architectures used in System on Chip designs. These architectures define technology independent standard bus protocol methodologies for easy integration of IPs within a System on Chip design. "CoreCOnnect" is mainly developed by IBM and integral part of PowerPC processor based System on Chip designs.
CoreConnect bus architecture has three parts:
1. PLB: Processor Local Bus
2. OPB: On chip Peripheral Bus
3. DCR: Device Control Register Bus
These specifications can be downloaded from IBM website.
"AMBA" stands for "Advanced Microcontroller (Microprocessor) Bus Architecture". AMBA specifiation is developed by ARM and extensively used in ARM based System on Chip designs.
AMBA has different versions as listed below from the lowest version:
1. ASP: AMBA Advanced System Bus
2. APB: AMBA Advanced Peripheral Bus
3. AHB: AMBA Advanced High performance Bus
4. AXI: AMBA Advanced eXtensible Interface
You can download AMBA specifications from ARM website also. You have to create an user account and follow the instructions.
Cheers !
Happy protocol reading !
System on Chip article links
Recently i came across some System on Chip (SoC) design related articles from design-reuse website. Enjoy good reading:
Getting the most from multiprocessor SoC design
SoC integration complexities rise
Challenges in developing a reusable IP core USB OTG IP case study
A Platform Based SoC Design Environment
Verification of IP Core Based SoC's
Analog IP Integration in SoC: Challenges and Solutions
Interface Synthesis in Multiprocessing Systems-On-Chips
Techniques for energy-efficient SoC design
Using a Versatile, Independent IP Platform for SoC Design
Meeting the challenges of 90nm SoC design
Top-down SoC Design Methodology
Benefits, risks in 90-nm SoC solutions
A Design of System on a Chip for Voice over Wireless LAN
SoC IP Interfaces and Infrastructure -- A Hybrid Approach
Getting the most from multiprocessor SoC design
SoC integration complexities rise
Challenges in developing a reusable IP core USB OTG IP case study
A Platform Based SoC Design Environment
Verification of IP Core Based SoC's
Analog IP Integration in SoC: Challenges and Solutions
Interface Synthesis in Multiprocessing Systems-On-Chips
Techniques for energy-efficient SoC design
Using a Versatile, Independent IP Platform for SoC Design
Meeting the challenges of 90nm SoC design
Top-down SoC Design Methodology
Benefits, risks in 90-nm SoC solutions
A Design of System on a Chip for Voice over Wireless LAN
SoC IP Interfaces and Infrastructure -- A Hybrid Approach
A PowerPC SOC IO Processor for RAID applications
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