5.2.6. Proper partitioning for synthesis
Properly partition the top level design
based on functionality. Keep related combinational logic in same module. It is
not recommended to add glue logic at top level of the module. Hierarchical
designs are good but unnecessary hierarchies may limit the optimizations across
the hierarchies. It is practically observed that deeper hierarchies cause
miserably failing boundary optimizations due to increased number of either
setup or hold fixing buffer insertion. In such cases ungrouping or flattening hierarchy
command can be used to flatten the unwanted hierarchies before compiling the
design to achieve better results.
References
[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005
[HM] Himanshu Bhatnagar, Advanced ASIC chip Synthesis Using Synopsys Design Compiler, Physical Compiler and PrimeTime, Kluwer Academic Publishers, Second edition, 2002
[DC] Design Compiler® User Guide, Version X-2005.09, September 2005
[RC] Using Encounter® RTL Compiler, Product Version 8.1.202, April 2009
[BH] J. Bhasker, Rakesh Chadha, Static Timing Analysis for Nanometer Designs A Practical Approach, 2009
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